-- Conversor 8bits para BCDlibrary ieee;
library ieee;
use ieee.std_logic_1164.all;

entity CONV_BCD is
	port
	(
		ENTRADA : in std_logic_vector(7 downto 0);
		SAIDA1 : out std_logic_vector(3 downto 0);
		SAIDA2 : out std_logic_vector(3 downto 0)
	);
end CONV_BCD;

architecture DT_FLOW of CONV_BCD is
signal CARRY1 : std_logic_vector(3 downto 0);
signal CARRY2 : std_logic_vector(3 downto 0);
begin
	
	process(ENTRADA)
	begin
	
	case ENTRADA(7 downto 4) is
		when "1010" =>
			CARRY2 <= "0001";
		when "1011" =>
			CARRY2 <= "0010";
		when "1100" =>
			CARRY2 <= "0011";
		when "1101" =>
			CARRY2 <= "0100";
		when "1110" =>
			CARRY2 <= "0101";
		when "1111" =>
			CARRY2 <= "0110";
		when others =>
			CARRY2 <= "0000";
	end case;
	
	case ENTRADA(3 downto 0) is
		when "1010" =>
			CARRY1 <= "0001";
		when "1011" =>
			CARRY1 <= "0010";
		when "1100" =>
			CARRY1 <= "0011";
		when "1101" =>
			CARRY1 <= "0100";
		when "1110" =>
			CARRY1 <= "0101";
		when "1111" =>
			CARRY1 <= "0110";
		when others =>
			CARRY1 <= "0000";
	end case;
	
	SAIDA1 <= CARRY1;
	SAIDA2 <= CARRY2;
	
	end process;

end DT_FLOW;